The QX6700 is based on the same 65nm manufacturing process as the other Core 2 processors. It incorporates a total of 8MB of L2 cache, as 4MB per pair of cores. Therein lies a problem: the two caches aren't interconnected. So each pair of cores shares 4MB of cache, and if processor A of core-pair X needs something from the cache of core-pair Y, it has to go out to memory. Juggling cache access to make sure the four cores don't get out of sync with each other is no trivial task.
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